論文発表

Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki and Ken Takeuchi, “Reliability Analysis of Scaled NAND Flash Memory based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test,” IEICE Transactions on Electronics, vol. E101-C, no. 4, pp. 243-252, April 2018.

Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui and Ken Takeuchi, “Analysis of SCM-based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size,” IEICE Transactions on Electronics, vol. E101-C, no. 4, pp. 253-262, April 2018.

Chihiro Matsui, Chao Sun and Ken Takeuchi, “Design of Hybrid SSDs with Storage Class Memory and NAND Flash Memory,” IEEE Proceedings, vol. 105, no. 9, pp. 1812-1821, July 2017.

Tomoaki Yamada, Chihiro Matsui and Ken Takeuchi, “Workload-Based Co-design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs,” IEICE Transactions on Electronics, vol. E100-C, no. 4, pp. 373-381, April 2017.

Yoshiaki Deguchi, Atsuro Kobayashi and Ken Takeuchi, “Write/Erase Stress Relaxation Effect on Data-Retention and Read-Disturb Errors in TLC NAND Flash Memory with Round-Robin Wear-Leveling,” Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, 04CE01, April 2017.

Chihiro Matsui, Tomoaki Yamada, Yusuke Sugiyama, Yusuke Yamaga and Ken Takeuchi, “Optimal memory configuration analysis on tri-hybrid solid-state drive with storage class memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash memory,” Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, 04CE02, April 2017.

Chihiro Matsui, Asuka Arakawa, Chao Sun and Ken Takeuchi, “Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD,” IEEE Transactions on VLSI Systems, vol. 25, no. 2, pp. 510-519, August 2016.

Tomoya Ishii, Sheyang Ning, Masahiro Tanaka, Kota Tsurumi and Ken Takeuchi, “Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications,” IEEE J. of Solid-State Circuits, vol. 51, no. 10, pp. 2389-2397, October 2016.

Chao Sun, Member, Shun Okamoto, Shogo Hachiya, Tomoaki Yamada and Ken Takeuchi, “Design Guidelines of Storage Class Memory/Flash Hybrid Solid-State Drive Considering System Architecture, Algorithm and Workload Characteristic,” IEEE Transactions on Consumer Electronics, vol. 62, no. 3, pp. 267-274, August 2016.

Masafumi Doi, Tsukasa Tokutomi, Shogo Hachiya, Atsuro Kobayashi, Shuhei Tanakamaru, Sheyang Ning, Tomoko Ogura Iwasaki and Ken Takeuchi, “Quick-Low-Density Parity Check (LDPC) and Dynamic Threshold Voltage (VTH) Optimization in 1Xnm Triple-Level Cell (TLC) NAND Flash Memory with Comprehensive Analysis of Endurance, Retention-Time and Temperature Variation,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 8, 084201, July 2016.

Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes and Ken Takeuchi, “Reset-Check-Reverse-Flag Scheme on NRAM with 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory,” IEEE J. of Solid-State Circuits, vol. 51, no. 8, pp. 1938-1951, August 2016.

Hirofumi Takishita, Shuhei Tanakamaru, Sheyang Ning and Ken Takeuchi, “Trade-off of Performance, Reliability and Cost of SCM/NAND Flash Hybrid SSD,” IEICE Transactions on Electronics, vol. E99-C, vol. 4, pp. 444-451, April 2016.

Senju Yamazaki, Tomoko Ogura Iwasaki, Shogo Hachiya, Tomonori Takahashi and Ken Takeuchi, “A 72% Error Reduction Scheme Based on Temperature Acceleration for Long-Term Data Storage Applications: Cold Flash and Millennium Memories,” Solid-State Electronics, vol. 121, pp.25-33, July 2016.

Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro1, Tadahiro Kuroda and Ken Takeuchi, “An Inductively-Powered Wireless Solid-State Drive System with Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 51, no. 4, pp. 1041-1050, April 2016.

Ken Takeuchi, “Memory System Architecture for the Data Centric Computing,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EA02, February 2016.

Masahiro Tanaka, Shogo Hachiya, Tomoya Ishii, Sheyang Ning, Kota Tsurumi and Ken Takeuchi, “0.6-1.0 V Operation Set/Reset Voltage (3V) Generator for 3D-integrated ReRAM and NAND flash Hybrid Solid-State Drive,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EE07, March 2016.

Sheyang Ning, Tomoko Ogura Iwasaki, Shogo Hachiya, Glen Rosendale, Monte Manning, Darlene Viviani, Thomas Rueckes and Ken Takeuchi, “Carbon Nanotube Memory Cell Array Program Error Analysis and Tradeoff between Reset Voltage and Verify Pulses,” Japanese Journal of Applied Physics (JJAP), vol. 55, no. 4S, 04EE01, February 2016.

Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita and Ken Takeuchi, “Understanding Relation Between Performance and Reliability of NAND Flash / SCM Hybrid Solid-State Drive (SSD),” IEEE Transactions on VLSI Systems, vol. 24, no. 6, pp. 2208 – 2219, June 2016.

Tomoko Ogura Iwasaki, Sheyang Ning, Hiroki Yamazawa and Ken Takeuchi,　“Array-level Stability Enhancement of 50nm AlxOy ReRAM,” Solid-State Electronics, vol. 114, pp. 1-8, December 2015.

Sheyang Ning, Tomoko Ogura Iwasaki, Kazuya Shimomura, Koh Johguchi, Eisuke Yanagizawa, Glen Rosendale, Monte Manning, Darlene Viviani, Thomas Rueckes and Ken Takeuchi,　“Investigation and Improvement of Verify-program in Carbon Nanotube Based Non-volatile Memory,” IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2837-2844, September 2015.