論文発表

Shinji Noda, Teruyoshi Hatanaka, Kousuke Miyaji, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi,　“A 1.2V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized VTH at Each Pump Stage for Ferroelectric (Fe)-NAND Flash Memories,” Japanese Journal of Applied Physics (JJAP), vol. 49, no.4, pp. 04DD10-04DD15, April 2010.

Teruyoshi Hatanaka, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi,　“A Negative Word-line Voltage Negatively-Incremental Erase Pulse Scheme with　ΔVTH=1/6 ΔVERASE for Enterprise Solid-State Drive (SSD) Application Ferroelectric (Fe)-NAND Flash Memories,” Japanese Journal of Applied Physics (JJAP),vol. 49, no.4, pp. 04DD08-04DD13, April 2010.

Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories,” IEICE Transactions on Electronics, vol. E93-C, no.3, pp. 317-323, March 2010.

Tsuyoshi Sekitani, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Siegfried Bauer, Ken Takeuchi, Makoto Takamiya, Takayasu Sakurai and Takao Someya, “Organic Nonvolatile Memory Transistors for Flexible Sensor Arrays,” Science, vol. 326, no. 5959, pp. 1516-1519, December 2009.

ShouyuWang, Mitue Takahashi, Qiu-Hong Li, Ken Takeuchi and Shigeki Sakai, “Operational method of a ferroelectric (Fe)-NAND flash memory array,” Semiconductor Science and Technology, 105029, 24, October 2009.

Ken Takeuchi, “Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD),” IEEE J. of Solid-State Circuits, vol. 44, no. 4, pp. 1227-1234, April 2009.

Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa and Shigeo Ohshima, “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10Mbyte/sec Program Throughput,” IEEE J. of Solid-State Circuits, vol. 42, no. 1, pp. 219-232, January 2007.

Kenichi Imamiya, Hiroshi Nakamura, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader and Jian J. Chen, “A 125-mm2 1-Gb NAND Flash Memory with 10MByte/sec Program Speed,” IEEE J. of Solid-State Circuits, vol. 37, no. 11, pp. 1493-1501, February 2002.

Ken Takeuchi and Tomoharu Tanaka, “A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 36, no. 5, pp. 744-751, May 2001.

Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, and Koji Sakui, “A Source-line Programming Scheme for Low Voltage Operation NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 35, no. 5, pp. 672-681 May 2000.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, and Koji Sakui, “A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technology,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1536-1542, November 1999.

Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, and Koji Sakui, “A Negative Vth Cell Architecture for Highly Scalable, Excellently Noise-Immune, and Highly Reliable NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 34, no. 5, pp. 675-684, June 1999.

Ken Takeuchi, Tomoharu Tanaka, and Toru Tanzawa, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 33, no. 8, pp. 1228-1238, August 1998.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seeichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, and Kazunori Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories,” IEEE J. of Solid-State Circuits, vol. 32, no. 5, pp. 662-669, May 1997.

Ken Takeuchi, Tomoharu Tanaka, and Hiroshi Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 31, no. 4, pp. 602-609, April 1996.

Ken Takeuchi, Tomoharu Tanaka, and Hiroshi Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEICE Transactions on Electronics, vol. E79-C, no. 7, pp. 1013-1020, July 1996.

Toshiharu Saiki, Ken Takeuchi, Kazuhiro Ema, Makoto Kuwata-Gonokami, K. Ohkawa, and T. Mitsuyu, “Free induction decay and quantum beat of excitons in ZnSe,” Journal of Crystal Growth, vol. 138, pp.805-808, April 1994.

Toshiharu Saiki, Ken Takeuchi, Makoto Kuwata-Gonokami, T. Mitsuyu and K. Ohkawa, “Giant excitonic optical nonlinearity in ZnSe grown by molecular beam epitaxy,” Journal of Crystal Growth, vol. 117, pp. 802-805, February 1992.

Toshiharu Saiki, Ken Takeuchi, Makoto Kuwata-Gonokami, T. Mitsuyu and K. Ohkawa, “Giant nonlinearity phase shift at exciton resonance in ZnSe,” Applied Physics Letter, vol. 60, no. 2, pp. 192-194, February 1992.