論文発表

Teruyoshi Hatanaka and Ken Takeuchi, “NAND Controller System with Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD,” IEEE J. of Solid-State Circuits, vol. 47, no. 6, pp. 1460-1468, June 2012.

Kousuke Miyaji, Yasuhiro Shinozuka, Shinji Miyano and Ken Takeuchi, “Near Threshold Voltage Word-line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM,” IEEE Transactions on Circuits and Systems I, vol. 59, no. 8, pp. 1635-1643, August 2012.

Xizhen Zhang, Mitsue Takahashi, Ken Takeuchi, and Shigeki Sakai,　“64 kbit Ferroelectric-Gate-Transistor-Integrated NAND Flash Memory with 7.5 V Program and Long Data Retention,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD01, April 2012.

Koh Johguchi, Teruyoshi Hatanaka and Ken Takeuchi,　“Through-Silicon-Via (TSV) Design with Clustering Structure and Adaptive TSV Control for 3D Solid-State-Drive Boost Converter System,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BE02, February 2012.

Kousuke Miyaji, Chinglin Hung and Ken Takeuchi,　“Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in sub-20nm Bulk/SOI NAND Flash Memory,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD12, April 2012.

Kazuhide Higuchi, Kousuke Miyaji, Koh Johguchi and Ken Takeuchi,　“Endurance Enhancement and High Speed Set/Reset of 50nm Generation HfO2–based Resistive Random Access Memory (ReRAM) Cell by Intelligent Set/Reset Pulse Shape Optimization and Verify Scheme,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 2, pp. 02BD07, February 2012.

Kousuke Miyaji, Yasuhiro Shinozuka and Ken Takeuchi,　“Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-side Assisted Erase Scheme Using Minimum Channel Length/Width Standard CMOS Single Transistor Cell,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD02, April 2012.

Kousuke Miyaji, Kentaro Honda, Shuhei Tanakamaru, Shinji Miyano and Ken Takeuchi, “Analysis of Operation Margin and Read Speed in 6T- and 8T-SRAM with Local Electron Injected Asymmetric Pass Gate Transistor,” IEICE Transactions on Electronics, vol. E95-C, no. 4, pp. 564-571, April 2012.

Kousuke Miyaji, Ryoji Yajima, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Initialize & and Weak-Program Erasing Scheme and Single-Pulse Programming Scheme for High-Performance and High-Reliability Ferroelectric NAND Flash Solid-State Drive,” IEICE Transactions on Electronics, vol. E95-C, no. 4, pp. 609-616, April 2012.

Shuhei Tanakamaru, Chinglin Hung and Ken Takeuchi, “Highly Reliable Lower Power Solid-State Drives (SSDs) Embedded with and Intelligent NAND Flash Memory Controller with Asymmetric Coding and Stripe Pattern Elimination Algorithm,” IEEE J. of Solid-State Circuits, vol. 47, no. 1, pp. 85-96, January 2012.

Shuhei Tanakamaru and Ken Takeuchi, “A 0.5V Operation VTH Loss Compensated DRAM Word-line Booster Circuit for Ultra-Low Power VLSI Systems,” IEEE J. of Solid-State Circuits, vol. 46, no. 10, pp. 2406-2415, October 2011.

Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda, Shinji Miyano and Ken Takeuchi, “Improvement of Read Margin and its Distribution by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection,” IEEE J. of Solid-State Circuits, vol. 46, no. 9, pp. 2180-2188, September 2011.

Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “1.8V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND,” IEEE J. of Solid-State Circuits, vol. 46, no. 6, pp. 1478-1487, June 2011.

Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Improvement of Read Disturb, Program Disturb and Data Retention by Memory Cell VTH Optimization of Ferroelectric (Fe)-NAND Flash Memories for Highly Reliable and Low Power Enterprise Solid-State Drives (SSDs),” IEICE Transactions on Electronics, vol. E94-C, no. 4, pp. 539-547, April 2011.

Mayumi Fukuda, Kazuhide Higuchi and Ken Takeuchi, “Non-volatile RAM and NAND Flash Memory-Integrated Solid-State Drives (SSDs) with Adaptive Codeword ECC for 3.6-Times Acceptable Raw Bit Error Rate Enhancement and 97% Power Reduction,” Japanese Journal of Applied Physics (JJAP), vol. 50, no.4, pp. 04DE09, April 2011.

Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD,” Solid-State Electronics, vol. 58, no. 1, pp. 34-41, April 2011.

Shuhei Tanakamaru, Mayumi Fukuda, Kazuhide Higuchi, Atsushi Esumi, Mitsuyoshi Ito, Kai Li and Ken Takeuchi, “Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs,” Solid-State Electronics, vol. 58, no. 1, pp. 2-10, April 2011.

Koh Johguchi, Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku, Makoto Takamiya, Takayasu Sakurai and Ken Takeuchi, “Through-Silicon-Via (TSV) design for a 3D-Solid-State-Drive (SSD) System with Boost Converter in a Package,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 269-277, February 2011.

Shuhei Tanakamaru, Teruyoshi Hatanaka, Ryoji Yajima, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “A 0.5-V 6-Transistor Static Random Access Memory with Ferroelectric-Gate Field Effect Transistors,” Japanese Journal of Applied Physics (JJAP), vol. 49, no. 12, pp. 121501-121509, December 2010.

Teruyoshi Hatanaka, Ryoji Yajima, Takeshi Horiuchi, Shouyu Wang, Xizhen Zhang, Mitsue Takahashi, Shigeki Sakai and Ken Takeuchi, “Ferroelectric (Fe)-NAND Flash Memory with Batch Write Algorithm and Smart Data Store to the Non-volatile Page Buffer for Data Center Application High Speed and Highly Reliable Enterprise Solid-State Drives (SSD),” IEEE J. of Solid-State Circuits, vol. 45, no. 10, pp. 2156-2164, October 2010.