論文発表

Hiroki Aihara, Kyosuke Maeda, Shun Suzuki and Ken Takeuchi, “Extremely Biased Error Correction Method to Reduce Read Disturb Errors of 3D-TLC NAND Flash Memories by 60%,” IEEE International Memory Workshop Poster, May 18, 2020.

Yusaku Hine, Reika Kinoshita, Yoshiki Kakuta and Ken Takeuchi, “Data Allocation Algorithm based on Write and Read Frequency for Double Asymmetric-latency SCM SSD,” IEEE International Memory Workshop Poster, May 20, 2020.

Masaki Abe, Chihiro Matsui, Keita Mizushina, Shun Suzuki and Ken Takeuchi, “Computational Approximate Storage with Neural Network-based Error Patrol of 3D-TLC NAND Flash Memory for Machine Learning Applications,” IEEE International Memory Workshop Poster, May 20, 2020.

Chihiro Matsui and Ken Takeuchi, “ReRAM Cell Reliability Variation Tolerated High-Speed Approximate Storage for Machine Learning,” IEEE Symp. on Low-Power and High-Speed Chips and Systems (Cool Chips 23) Poster, April 15, 2020.

Yoshiki Kakuta, Reika Kinoshita, Hiroshi Kinoshita, Chihiro Matsui and Ken Takeuchi, “Real-time Error Monitoring System Considering Endurance and Data-retention Characteristics of TaOX-based ReRAM Storage with Workloads at Data Centers,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), August 13, 2020.

Tsubasa Yonai, Hiroshi Kinoshita, Ryutaro Yasuhara and Ken Takeuchi, “98% Endurance Error Reduction by Hard_Verify for 40nm TaOX-based ReRAM,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), August 11, 2020.

Reika Kinoshita, Atsuya Suzuki, Shouhei Fukuyama, Chihiro Matsui and Ken Takeuchi, “Workload-aware Data-eviction Self-adjusting System of Multi-SCM Storage to Resolve Trade-off between SCM Data-retention Error and Storage System Performance,” 25th Asia and South Pacific Design Automation Conference (ASP-DAC 2020), pp. 319-324, January 2020.

Shun Suzuki, Kyoji Mizoguchi, Hikaru Watanabe, Toshiki Nakamura, Yoshiaki Deguchi, Keita Mizushina and Ken Takeuchi, “Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing,” IEEE Asian Solid-State Circuits Conference (A-SSCC), November 6, 2019.

Koki Kamimura, Susumu Nohmi, Kenta Suzuki and Ken Takeuchi, “Parallel Product-Sum Operation Neuromorphic Systems with 4-bit Ferroelectric FET Synapses,” IEEE European Solid-State Device Research Conference (ESSDERC), pp. 178-181, September 2019.

Hiroshi Kinoshita, Shouhei Fukuyama, Tsubasa Yonai, Ryutaro Yasuhara and Ken Takeuchi, “85% Endurance Error Reduction by Changing Reset Voltage in 40nm TaOX-based ReRAM,” International Conference on Solid State Devices and Materials (SSDM), September, 2019.

Reika Kinoshita, Chihiro Matsui and Ken Takeuchi, “Maximizing Performance/cost of SSD Composed of Memory-type and Storage-type SCMs,” Flash Memory Summit, August, 2019.

Chihiro Matsui and Ken Takeuchi, “TaOx-based ReRAM for Variability-Aware Approximate Computing,” Flash Memory Summit, August, 2019.

Ken Takeuchi, “Non-volatile Memory Storage for Machine Learning,” IEEE SSCS VLSIedu, June 13, 2019.

Masaki Abe, Toshiki Nakamura and Ken Takeuchi, “Pre-shipment Data-retention/Read-disturb Lifetime Prediction & Aftermarket Cell Error Detection & Correction by Neural Network for 3D-TLC NAND Flash Memory,” IEEE Symp. on VLSI Technology, pp. 216-217, June 13, 2019.

Chihiro Matsui, Shouhei Fukuyama, Atsuna Hayakawa and Ken Takeuchi, “Application-Induced Cell Reliability Variability-Aware Approximate Computing in TaOX-based ReRAM Data Center Storage for Machine Learning,” IEEE Symp. on VLSI Technology, pp. 234-235, June 13, 2019.

Kyosuke Maeda, Kyoji Mizoguchi and Ken Takeuchi, “Less Reliable Page Error Reduction for 3D-TLC NAND Flash Memories with Data Overhead Reduction by 40% and Data-retention Time Increase by 5.0x,” Silicon Nanoelectronics Workshop (SNW), June 9-10, 2019.

Daiki Kojima, Toshiki Nakamura and Ken Takeuchi, “Error Crrection for Read-hot Data in 3D-TLC NAND Flash by Read-disturb Modeled Artificial Neural Network Coupled LDPC ECC,” Silicon Nanoelectronics Workshop (SNW), June 9-10, 2019.

Yoshiki Takai, Mamoru Fukuchi, Reika Kinoshita, Chihiro Matsui and Ken Takeuchi, “Analysis on Heterogeneous SSD Configuration with Quadruple-Level Cell (QLC) NAND Flash Memory,” IEEE International Memory Workshop, May 2019.

Toshiki Nakamura, Shun Suzuki and Ken Takeuchi, “Data Pattern & Memory Variation Aware Fine-Grained ECC Optimized by Neural Network for 3D-TLC NAND Flash Memories with 2.0x Data-retention Time Extension and 30% Parity Overhead Reduction,” IEEE International Memory Workshop, May 2019.

Chihiro Matsui and Ken Takeuchi, “Self-Determining Resource Control in Multi-Tenant Data Center Storage with Future NV Memories,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2019.