Kazuhide Higuchi, Chihiro Matsui and Ken Takeuchi, “Investigation of Memory Non-Ideality Impacts on Non-Volatile Memory Based Computation-in-Memory AI Inference by Comprehensive Simulation Platform,” IEEE Silicon Nanoelectronics Workshop (SNW) Poster, pp. 57-58, June 11-12, 2022.
Chihiro Matsui, Eitaro Kobayashi, Kasidit Toprasertpong, Shinichi Takagi and Ken Takeuchi, “Versatile FeFET Voltage-Sensing Analog CiM for Fast & Small-Area Hyperdimensional Computing,” IEEE International Symposium on Circuits and Systems (ISCAS), June 1, 2022.
Naoko Misawa, Kenta Taoka, Chihiro Matsui and Ken Takeuchi, “Domain Specific ReRAM Computation-in-Memory Design Considering Bit Precision and Memory Errors for Simulated Annealing,” IEEE International Symposium on Circuits and Systems (ISCAS), June 1, 2022.
Shinsei Yoshikiyo, Naoko Misawa, Chihiro Matsui and Ken Takeuchi, “Edge Computation-in-Memory for In-Situ Class-Incremental Learning with Knowledge Distillation,” IEEE International Symposium on Circuits and Systems (ISCAS), May 31, 2022.
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui and Ken Takeuchi, “Edge Retraining of FeFET LM-GA CiM for Write Variation & Reliability Error Compensation,” IEEE International Memory Workshop, May 18, 2022.
Yuya Ichikawa, Akira Goda, Chihiro Matsui and Ken Takeuchi, “Non-volatile Memory Application to Quantum Error Correction with Non-uniformly Quantized CiM,” IEEE International Memory Workshop Poster, May 16, 2022.
Naoko Misawa, Chihiro Matsui and Ken Takeuchi, “Compact and Tunable ReRAM Computation-in-Memory for Log-encoding Simulated Annealing,” IEEE Symp. on Low-Power and High-Speed Chips and Systems (Cool Chips 25) Poster, April 20, 2022.
Kazuhide Higuchi, Chihiro Matsui, Naoko Misawa and Ken Takeuchi, “Simulation Platform of Computation-in-Memory with Memory Device Non-idealities for DNN,” IEEE Symp. on Low-Power and High-Speed Chips and Systems (Cool Chips 25) Poster, April 20, 2022.
Akira Goda, Chihiro Matsui and Ken Takeuchi, “Inter Spike Interval and Stochasticity Engineering of Floating Gate Technology-based Neurons for Spiking Neural Network Hardware”, 6th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2022, March 8, 2022.
Kasidit Toprasertpong, Eishin Nako, Zeyu Wang, Chihiro Matsui, Ryosho Nakane, Ken Takeuchi, Mitsuru Takenaka and Shinichi Takagi, “HfZrO2-based ferroelectric FETs for emerging computing technologies,” 2021 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES (IWDTF), November 15, 2021. 【招待講演】
Ken Takeuchi, “Co-design of non-volatile memory devices, circuits and systems in AI era,” 2021 International Workshop on DIELECTRIC THIN FILMS FOR FUTURE ELECTRON DEVICES (IWDTF), November 14, 2021. 【基調講演】
Ken Takeuchi, “How to heterogeneously integrate PIM for Edge AI?,” IEEE Asian Solid-State Circuits Conference (A-SSCC) Panel PIM (Processing in Memory) will go with Analog or Digital?, November 8, 2021. 【招待講演】
Chihiro Matsui, Kazuhide Higuchi, Shunsuke Koshino and Ken Takeuchi, “Event-Driven SRAM Computation-in-Memory with Partitioned WL Activation for 3D Heterogeneous Integration of Event-based Vision Sensor”, International Conference on Solid State Devices and Materials (SSDM), September 7, 2021.
Naoko Misawa, Kenta Taoka, Chihiro Matsui and Ken Takeuchi, “Small Array Area, Memory Error Tolerant ReRAM Computation-in-Memory with Log-encoding Simulated Annealing for Combinational Optimization Problems”, International Conference on Solid State Devices and Materials (SSDM), September 8, 2021.
Kazuhide Higuchi, Chihiro Matsui, Naoko Misawa and Ken Takeuchi, “Comprehensive Computation-in-Memory Simulation Platform with Non-volatile Memory Non-Ideality Consideration for Deep Learning Applications”, International Conference on Solid State Devices and Materials (SSDM), September 8, 2021.
Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, and and Ken Takeuchi, “Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing,” IEEE Symp. on VLSI Technology, June 18, 2021.
Ken Takeuchi, “Memory Circuit & Technology Co-Design for AI Applications,” Silicon Nanoelectronics Workshop (SNW), June 13, 2021. 【基調講演】
Daiki Kojima and Ken Takeuchi, “Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory,” IEEE International Symposium on Circuits and Systems (ISCAS), May 27, 2021.
Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui and Ken Takeuchi, “BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads,” IEEE International Symposium on Circuits and Systems (ISCAS), May 26, 2021.
Kenta Taoka, Naoko Misawa, Shunsuke Koshino, Chihiro Matsui and Ken Takeuchi, “Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory,” IEEE International Memory Workshop, May 21, 2021.
