Chao Sun, Asuka Arakawa and Ken Takeuchi, “SEA-SSD: A Storage Engine Assisted SSD with Application-Coupled Simulation Platform,” IEEE Transactions on Circuits and Systems I, vol. 62, no. 1, pp. 120-129, January 2015.

Chao Sun, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi and Ken Takeuchi, “Cost, Capacity and Performance Analyses for Hybrid SCM/NAND Flash SSD,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 8, pp. 2360 – 2369, August 2014.

Koh Johguchi, Kasuaki Yoshioka and Ken Takeuchi, “NAND Phase Change Memory with Block-Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance,” IEICE Transactions on Electronics, vol. E97-C, no. 4, pp. 351-359, April 2014.

Koh Johguchi, Toru Egami, Kousuke Miyaji and Ken Takeuchi, “A Temperature Tracking Read Reference Current and Write Voltage Generator for Multi-Level Phase Change Memories,” IEICE Transactions on Electronics, vol. E97-C, no. 4, pp. 342-350, April 2014.

Masafumi Doi, Shuhei Tanakamaru and Ken Takeuchi, “A Scaling Scenario of Asymmetric Coding to reduce both Data Retention and Program Disturbance of NAND Flash Memories,” Solid-State Electronics, vol. 92, pp. 63-69, April 2014.

Toru Egami, Koh Johguchi, Senju Yamazaki and Ken Takeuchi,　“Investigation of Multi-Level-Cell and SET Operations on Super-Lattice Phase Change Memories,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04ED02, April 2014.

Sheyang Ning, Tomoko Ogura Iwasaki and Ken Takeuchi,　“50nm AlxOy ReRAM Array Program Bit Error Reduction and High Temperature Operation,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04ED09, April 2014.

Shogo Hachiya, Koh Johguchi, Kousuke Miyaji and Ken Takeuchi,　“Hybrid Triple-Level-Cell (TLC) /Multi-Level-Cell (MLC) NAND Flash Storage Array with Chip Exchangeable Method,” Japanese Journal of Applied Physics (JJAP), vol. 53, 04EE04, April 2014.

Shuhei Tanakamaru, Masafumi Doi and Ken Takeuchi, “NAND Flash Memory / ReRAM Hybrid Unified Solid-State-Storage Architecture,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 4, pp. 1119-1132, April 2014.

Kousuke Miyaji, Yuki Yanagihara, Reo Hirasawa, Sheyang Ning and Ken Takeuchi,　“Control Gate Length, Spacing, Channel Hole Diameter and Stacked Layer Number Design for BiCS-Type 3D-Stackable NAND Flash Memory,” Japanese Journal of Applied Physics (JJAP), vol. 53, 024201, January 2014.

Kazuhide Higuchi, Tomoko Ogura Iwasaki and Ken Takeuchi, “Evaluation of Voltage vs. Pulse Width Modulation and Feedback during Set/Reset Verify-Programming to Achieve 10 Million Cycles for 50nm HfO2 ReRAM,” Solid-State Electronics, vol. 91, pp. 67-73, January 2014.

Ken Takeuchi, “NAND Flash Application and Solution,” IEEE Solid-State Circuits Magazine, vol. 5, no. 4, pp. 34-40, December, 2013.

Shuhei Tanakamaru, Yuki Yanagihara and Ken Takeuchi, “Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs),” IEEE J. of Solid-State Circuits, vol. 48, no. 11, pp. 1-14, November, 2013.

Chao Sun, Kousuke Miyaji, Koh Johguchi　and Ken Takeuchi, “A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD,” IEEE Transactions on Circuits and Systems I, vol. 61, no. 2, pp. 382-392, February 2014.

Ken Takeuchi, “Storage Class Memory & NAND Flash Memory Hybrid Solid-State Drives (SSD)” Electrochemical Society Meeting (ECS) Transactions, vol. 58, no. 5, pp 3-8, October 2013.

Kousuke Miyaji, Toshikazu Suzuki and Ken Takeuchi, “A 6T-SRAM with a Post-Process Electron Injection Scheme that Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy,” IEEE J. of Solid-State Circuits, vol. 48, no. 9, pp. 2239-2249, September, 2013.

Tomoko Ogura Iwasaki, Sheyang Ning and Ken Takeuchi,　“Forward and Reverse Biasing in Resistive Memories for Fast, Disturb-Free Read, and Verify,”Japanese Journal of Applied Physics (JJAP), vol. 52, 04CD12, April 2013.

Koh Johguchi, Toshimichi Shintani, Takahiro Morikawa, Kazuaki Yoshioka and Ken Takeuchi, “x10 Fast Write, 80% Energy Saving Temperature Control-ling Set Method for Multi-Level Cell Phase Change Memo-ries to Solve the Scaling Blockade,” Solid-State Electronics, vol. 81, pp. 78- 85, March 2013.

Shuhei Tanakamaru, Chinglin Hung and Ken Takeuchi, “Highly Reliable Lower Power Solid-State Drives (SSDs) Embedded with and Intelligent NAND Flash Memory Controller with Asymmetric Coding and Stripe Pattern Elimination Algorithm,” IEEE J. of Solid-State Circuits, vol. 47, no. 1, pp. 85-96, January 2012.

Ken Takeuchi, Teruyoshi Hatanaka and Shuhei Tanakamaru,　“Highly Reliable, High Speed and Low Power NAND Flash Memory-Based Solid State Drives (SSDs),” IEICE Electronics Express (ELEX), vol. 9, no. 8, pp. 779-794, August 2012. 【招待論文】