Journal Papers
  • Chihiro Matsui and Ken Takeuchi, “Non-volatile memory system design of edge server and cloud centralized server for multiple-tier 5G network,” Japanese Journal of Applied Physics (JJAP), vol. 60, pp. SBBB05, March 16, 2021.

  • Shun Suzuki, Hiroki Aihara and Ken Takeuchi, “Privacy Protection NAND Flash System with Flexible Data-Lifetime Control by In-3D Vertical Cell Processing,” IEEE J. of Solid-State Circuits, June 2020.

  • Hiroshi Kinoshita, Tsubasa Yonai and Ken Takeuchi, “85% Endurance Error Reduction and Data-retention Lifetime Enhancement by Changing Reset Voltage in 40nm TaOx-based ReRAM,” Japanese Journal of Applied Physics (JJAP), vol. 59, SGGB14, April 2020.

  • Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita and Ken Takeuchi, “nalysis on Hybrid SSD Configuration with Emerging Non-volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs),” IEICE Transactions on Electronics, E103-C, No.4, April 2020.

  • Mamoru Fukuchi, Chihiro Matsui and Ken Takeuchi, “System Performance Comparison of 3D Charge-trap TLC NAND Flash and 2D Floating-gate MLC NAND Flash based SSDs,” IEICE Transactions on Electronics, E103-C, No.4, April 2020.

  • Chihiro Matsui and Ken Takeuchi, “Step-by-Step Design of Memory Hierarchy for Heterogeneously-integrated SCM/NAND Flash Storage,” Integration, the VLSI Journal, vol. 69, pp. 62-74, September 2019.

  • Chihiro Matsui and Ken Takeuchi, “Dynamic Adjustment of Storage Class Memory (SCM) Capacity in Memory-Resource Disaggregated Hybrid Storage with SCM and NAND Flash Memory,” IEEE Transactions on VLSI Systems, vol. 27, no. 8, pp. 1799-1810, August 2019.

  • Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa and Ken Takeuchi, “3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition,” IEEE J. of Solid-State Circuits, vol. 54, no. 6, pp. 1800-1811, March 2019.

  • Toshiki Nakamura, Yoshiaki Deguchi and Ken Takeuchi, “Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 54, no. 3, pp. 745-754, March 2019.

  • Yoshiaki Deguchi, Shun Suzuki and Ken Takeuchi, “Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2D and 3D-TLC NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 53, no. 10, pp. 2917-2926, October 2018.

  • Hikaru Watanabe, Yoshiaki Deguchi, Atsuro Kobayashi, Chihiro Matsui and Ken Takeuchi, “System-level Read Disturb Suppression Techniques of TLC NAND Flash Memories for Read-Hot/Cold Data Mixed Applications,” Solid-State Electronics, vol. 147, pp. 63-77, September 2018.

  • Yukiya Sakaki, Tomoaki Yamada, Chihiro Matsui, Yusuke Yamaga and Ken Takeuchi, “Performance analysis of 3D-triple-level cell and 2D-multi-level cell NAND flash hybrid solid-state drives,” Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, pp. 04FE03, April 2018.

  • Chihiro Matsui, Reika Kinoshita and Ken Takeuchi, “Analysis on applicable ECC strength of SCM and NAND flash in hybrid storage,” Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, pp. 04FE01, February 2018.

  • Yusuke Yamaga, Chihiro Matsui, Yukiya Sakaki and Ken Takeuchi, “Reliability Analysis of Scaled NAND Flash Memory based SSDs with Real Workload Characteristics by Using Real Usage-Based Precise Reliability Test,” IEICE Transactions on Electronics, vol. E101-C, no. 4, pp. 243-252, April 2018.

  • Hirofumi Takishita, Yutaka Adachi, Chihiro Matsui and Ken Takeuchi, “Analysis of SCM-based SSD Performance in Consideration of SCM Access Unit Size, Write/Read Latencies and Application Request Size,” IEICE Transactions on Electronics, vol. E101-C, no. 4, pp. 253-262, April 2018.

  • Chihiro Matsui, Chao Sun and Ken Takeuchi, “Design of Hybrid SSDs with Storage Class Memory and NAND Flash Memory,” IEEE Proceedings, vol. 105, no. 9, pp. 1812-1821, July 2017.

  • Tomoaki Yamada, Chihiro Matsui and Ken Takeuchi, “Workload-Based Co-design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs,” IEICE Transactions on Electronics, vol. E100-C, no. 4, pp. 373-381, April 2017.

  • Yoshiaki Deguchi, Atsuro Kobayashi and Ken Takeuchi, “Write/Erase Stress Relaxation Effect on Data-Retention and Read-Disturb Errors in TLC NAND Flash Memory with Round-Robin Wear-Leveling,” Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, 04CE01, April 2017.

  • Chihiro Matsui, Tomoaki Yamada, Yusuke Sugiyama, Yusuke Yamaga and Ken Takeuchi, “Optimal memory configuration analysis on tri-hybrid solid-state drive with storage class memory (SCM) and multi-level cell (MLC)/triple-level cell (TLC) NAND flash memory,” Japanese Journal of Applied Physics (JJAP), vol. 56, no. 4S, 04CE02, April 2017.

  • Chihiro Matsui, Asuka Arakawa, Chao Sun and Ken Takeuchi, “Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD,” IEEE Transactions on VLSI Systems, vol. 25, no. 2, pp. 510-519, August 2016.

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