Chihiro Matsui, Eitaro Kobayashi, Naoko Misawa and Ken Takeuchi, “Comprehensive analysis on error-robustness of FeFET computation-in-memory for hyperdimensional computing,” Japanese Journal of Applied Physics (JJAP), vol. 62, pp. SC1053, February 6, 2023.
Kazuhide Higuchi, Tomoki Kobayashi, Naoko Misawa, Chihiro Matsui and Ken Takeuchi, “Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory,” Japanese Journal of Applied Physics (JJAP), vol. 62, pp. SC1068, February 14, 2023.
Akira Goda, Chihiro Matsui and Ken Takeuchi, “A Stochastic Leaky-Integrate-and-Fire Neuron Model With Floating Gate-Based Technology for Fast and Accurate Population Coding,” IEEE Journal of the Electron Devices Society, vol. 10, pp.861-869, September 13, 2022.
Chihiro Matsui and Ken Takeuchi, “Heterogeneous Integration of Precise and Approximate Storage for Error-tolerant Workloads,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, September 5, 2022.
Chihiro Matsui, Kazuhide Higuchi, Shunsuke Koshino and Ken Takeuchi, “Event Data-based Computation-in-Memory (CiM) Configuration by Co-designing Integrated In-Sensor & CiM Computing for Extremely Energy Efficient Edge Computing,” Japanese Journal of Applied Physics (JJAP), vol. 61, pp. SC1085, April 7, 2022.
Kazuhide Higuchi, Chihiro Matsui, Naoko Misawa and Ken Takeuchi, “Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications,” Japanese Journal of Applied Physics (JJAP), vol. 61, pp. SC1054, February 21, 2022.
Naoko Misawa, Kenta Taoka, Chihiro Matsui and Ken Takeuchi, “97.6% array area reduction, ReRAM computation-in-memory with hyperparameter optimization based on memory bit-error rate and bit precision of log-encoding simulated annealing,” Japanese Journal of Applied Physics (JJAP), vol. 61, pp. SC1001, February 8, 2022.
Chihiro Matsui and Ken Takeuchi, “Non-volatile memory system design of edge server and cloud centralized server for multiple-tier 5G network,” Japanese Journal of Applied Physics (JJAP), vol. 60, pp. SBBB05, March 16, 2021.
Shun Suzuki, Hiroki Aihara and Ken Takeuchi, “Privacy Protection NAND Flash System with Flexible Data-Lifetime Control by In-3D Vertical Cell Processing,” IEEE J. of Solid-State Circuits, June 2020.
Hiroshi Kinoshita, Tsubasa Yonai and Ken Takeuchi, “85% Endurance Error Reduction and Data-retention Lifetime Enhancement by Changing Reset Voltage in 40nm TaOx-based ReRAM,” Japanese Journal of Applied Physics (JJAP), vol. 59, SGGB14, April 2020.
Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita and Ken Takeuchi, “nalysis on Hybrid SSD Configuration with Emerging Non-volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs),” IEICE Transactions on Electronics, E103-C, No.4, April 2020.
Mamoru Fukuchi, Chihiro Matsui and Ken Takeuchi, “System Performance Comparison of 3D Charge-trap TLC NAND Flash and 2D Floating-gate MLC NAND Flash based SSDs,” IEICE Transactions on Electronics, E103-C, No.4, April 2020.
Chihiro Matsui and Ken Takeuchi, “Step-by-Step Design of Memory Hierarchy for Heterogeneously-integrated SCM/NAND Flash Storage,” Integration, the VLSI Journal, vol. 69, pp. 62-74, September 2019.
Chihiro Matsui and Ken Takeuchi, “Dynamic Adjustment of Storage Class Memory (SCM) Capacity in Memory-Resource Disaggregated Hybrid Storage with SCM and NAND Flash Memory,” IEEE Transactions on VLSI Systems, vol. 27, no. 8, pp. 1799-1810, August 2019.
Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa and Ken Takeuchi, “3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition,” IEEE J. of Solid-State Circuits, vol. 54, no. 6, pp. 1800-1811, March 2019.
Toshiki Nakamura, Yoshiaki Deguchi and Ken Takeuchi, “Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 54, no. 3, pp. 745-754, March 2019.
Yoshiaki Deguchi, Shun Suzuki and Ken Takeuchi, “Write and Read Frequency-Based Word-Line Batch VTH Modulation for 2D and 3D-TLC NAND Flash Memories,” IEEE J. of Solid-State Circuits, vol. 53, no. 10, pp. 2917-2926, October 2018.
Hikaru Watanabe, Yoshiaki Deguchi, Atsuro Kobayashi, Chihiro Matsui and Ken Takeuchi, “System-level Read Disturb Suppression Techniques of TLC NAND Flash Memories for Read-Hot/Cold Data Mixed Applications,” Solid-State Electronics, vol. 147, pp. 63-77, September 2018.
Yukiya Sakaki, Tomoaki Yamada, Chihiro Matsui, Yusuke Yamaga and Ken Takeuchi, “Performance analysis of 3D-triple-level cell and 2D-multi-level cell NAND flash hybrid solid-state drives,” Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, pp. 04FE03, April 2018.
Chihiro Matsui, Reika Kinoshita and Ken Takeuchi, “Analysis on applicable ECC strength of SCM and NAND flash in hybrid storage,” Japanese Journal of Applied Physics (JJAP), vol. 57, no. 4S, pp. 04FE01, February 2018.
