Yusuke Yamaga, Yoshiaki Deguchi, Shouhei Fukuyama and Ken Takeuchi, “5x Reliability Enhanced 40nm TaOx Approximate-ReRAM with Domain-Specific Computing for Real-time Image Recognition of IoT Edge Devices,” IEEE Symp. on VLSI Technology, pp. 109-110, June 20, 2018.
Yoshiaki Deguchi, Kazuki Maeda, Shun Suzuki, Toshiki Nakamura and Ken Takeuchi, “Error-Reduction Controller Techniques of TaOx-based ReRAM for Deep Neural Networks to Extend Data-Retention Lifetime by Over 1700x,” IEEE International Memory Workshop, pp. 1-4, May 2018.
Yoshiaki Deguchi and Ken Takeuchi, “3D-NAND Flash Solid-State Drive (SSD) for Deep Neural Network Weight Storage of IoT Edge Devices with 700x Data-retention Lifetime Extention,” IEEE International Memory Workshop, pp. 1-4, May 2018.
Atsuna Hayakawa, Toshiki Nakamura, Yoshiaki Deguchi, Kazuki Maeda and Ken Takeuchi, “Data-aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network,” IEEE International Symposium on Circuits and Systems (ISCAS) Poster, pp. 1-5, May 2018.
Mamoru Fukuchi, Yukiya Sakaki, Chihiro Matsui and Ken Takeuchi, “20% System-performance Gain of 3D Charge-trap TLC NAND Flash over 2D Floating-gate MLC NAND Flash for SCM/NAND Flash Hybrid SSD,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018.
Keita Mizushina, Toshiki Nakamura, Yoshiaki Deguchi and Ken Takeuchi, “Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May 2018.
Chihiro Matsui and Ken Takeuchi, “3ASCA: Application-Aware Autonomous SCM Capacity Adjustment for SCM and NAND Flash Pooled Storage,” IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, May 2018.
Yutaka Adachi, Chihiro Matsui and Ken Takeuchi, “Double Asymmetric-latency Storage Class Memories (SCMs) for Fast-Write SCM, Fast-Read SCM & NAND Flash Hybrid SSDs,” 2018 International Symposium on VLSI Design, Automation and Test (2018 VLSI-DAT), pp. 1-4, April 2018.
Kenta Suzuki, Masahiro Tanaka, Kota Tsurumi and Ken Takeuchi, “43 % Reduced Program Time, 23 % Energy Efficient ReRAM Boost Converter with PMOS Switching Transistor and Boosted Buffer Circuit for ReRAM and NAND Flash Hybrid SSDs,” International Conference on Electronic Packageing (ICEP), pp. 164-169, April 2018.
Masaru Nakanishi, Yutaka Adachi, Chihiro Matsui, Yusuke Sugiyama and Ken Takeuchi, “Application-oriented Wear-leveling Optimization of 3D TSV-integrated Storage Class Memory-based Solid State Drives,” International Conference on Electronic Packageing (ICEP), pp. 27-32, April 2018.
Toshiki Nakamura, Yoshiaki Deguchi and Ken Takeuchi, “9.1x Error Acceptable Adaptive Artificial Neural Network Coupled LDPC ECC for Charge-trap and Floating-gate 3D-NAND Flash Memories,” IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, April 10, 2018.
Shun Suzuki, Yoshiaki Deguchi, Toshiki Nakamura, Kyoji Mizoguchi and Ken Takeuchi, “Cross Error Elimination ECC by Horizontal Error Detection and Vertical-LDPC ECC to Increase Data-Retention Time by 230% and Acceptable Bit-Error Rate by 90% for 3D-NAND Flash SSDs,” IEEE International Reliability Physics Symposium (IRPS) Poster, P-MY.7-1 – P-MY.7-4, March 2018.
Shouhei Fukuyama, Kazuki Maeda, Ryutaro Yasuhara, Shinpei Matsuda and Ken Takeuchi, “Suppression of Endurance-stressed Data-retention Failures of 40nm TaOx-based ReRAM,” IEEE International Reliability Physics Symposium (IRPS) Poster, P-MY.4-1 – P-MY.4-5, March 2018.
Chihiro Matsui and Ken Takeuchi, “Application-optimized Non-volatile Memory Combination in Heterogeneously-integrated Disaggregated Storage,” 9th Non-Volatile Memories Workshop 2018 (NVMW) Poster, March 12, 2018.
Kyoji Mizoguchi, Shohei Kotaki, Yoshiaki Deguchi and Ken Takeuchi, “Lateral Charge Migration Suppression of 3D-NAND Flash by VTH Nearing for Near Data Computing,” IEEE International Electron Devices Meeting (IEDM), pp. 465-468, December 2017.
Ken Takeuchi, “Data-Aware NAND Flash Memory for Intelligent Computing with Deep Neural Network,” IEEE International Electron Devices Meeting (IEDM), pp. 665-668, December 2017. 【招待講演】
Chihiro Matsui and Ken Takeuchi, “Heterogeneous Storage with Storage Class Memories and NAND Flash Memory for Big and Fast Data Processing,” Phase Change Oriented Science (PCOS), November 17, 2017.【招待講演】
Yoshiaki Deguchi and Ken Takeuchi, “Word-line Batch VTH Modulation of TLC NAND Flash Memories for Both Write-Hot and Cold Data,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.161-164, November 8, 2017.
Hikaru Watanabe, Yoshiaki Deguchi and Ken Takeuchi, “MLC/3LC NAND Flash SSD Cache with Asymmetric Error Reduction Huffman Coding for Tiered Hierarchical Storage,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.157-160, November 8, 2017.
Takashi Inose, Seiichi Aritome, Ryutaro Yasuhara, Satoshi Mishima and Ken Takeuchi, “Study of Error Repeatability and Recovery in 40nm TaOx ReRAM,” IEEE European Solid-State Device Research Conference (ESSDERC), pp.10-13, September 12, 2017.
