Shigeki Sakai, Mitsue Takahashi, Ken Takeuchi, Qiu-Hong Li, Takeshi Horiuchi, Shouyu Wang, Kwi-Young Yun, Makoto Takamiya, and Takayasu Sakurai, “Highly Scalable Fe(Ferroelectric)-NAND Cell with MFIS(Metal-Ferroelectric-Insulator-Semiconductor) Structure for Sub-10nm Tera-Bit Capacity NAND Flash Memories,” IEEE Non-volatile Semiconductor Memory Workshop (NVSMW), pp. 103-104, May 2008.

Ken Takeuchi, “Circuit design of NAND flash memories,” International Symposium on Secure-Life Electronics, pp. 153-159, March 2008.

Ken Takeuchi, “NAND successful as a media for SSD,” IEEE International Solid-State Circuits Conference (ISSCC), Tutorial T-7, February 2008.【招待講演】

Ken Takeuchi, “Technology overview of flash memories,” SEMI Forum 2007, Memory symposium, June 2007.【招待講演】

Ken Takeuchi, “Technological and marketing trend of NAND flash memories,” SEMI Forum 2006, Memory symposium, June 2006. 【招待講演】

Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa and Shigeo Ohshima, “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10Mbyte/sec Program Throughput,” IEEE International Solid-State Circuits Conference (ISSCC), pp.144-145, February 2006.

Ken Takeuchi, “Technology trend of NAND flash memories,” SEMI Forum 2004, Memory symposium, June 2004.【招待講演】

Hiroshi Nakamura, Kenichi Imamiya, Toshihiko Himeno, Toshio Yamamura, Tamio Ikehashi, Ken Takeuchi, Kazushige Kanda, Koji Hosono, Takuya Futatsuyama, Koichi Kawai, Riichiro Shirota, Norihisa Arai, Fumitaka Arai, Kazuo Hatakeyama, Hiroaki Hazama, Masanobu Saito, Hisataka Meguro, Kevin Conley, Khandker Quader and Jian Chen, “A 125mm2 1Gb NAND Flash Memory with 10MB/s Program Throughput,” IEEE International Solid-State Circuits Conference (ISSCC), pp.106-107, February 2002.

Ken Takeuchi and Tomoharu Tanaka, “A Dual Page Programming Scheme for High-Speed Multi-Gb-Scale NAND Flash Memories,” IEEE Symp. on VLSI Circuits, pp.156-157, June 2000.

Shinji Satoh, Takuya Nakamura, Kazuhiro Shimizu, Ken Takeuchi, Hiroshi Iizuka, Seiichi Aritome, and Riichiro Shirota, “A Novel Gate-Offset NAND Cell (GOC-NAND) Technology Suitable for High-Density and Low-Voltage-Operation Flash Memories,” IEEE International Electron Devices Meeting (IEDM), pp. 271-274, December 1999.

Kenichi Imamiya, Yoshihisa Sugiura, Hiroshi Nakamura, Toshihiko Himeno, Ken Takeuchi, Tamio Ikehashi, Kazushige Kanda, Koji Hosono, Riichiro Shirota, Seiichi Aritome, Kazuhiro Shimizu, Kazuo Hatakeyama, and Koji Sakui, “A 130-mm2, 256-Mbit NAND Flash with Shallow Trench Isolation Technology,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 112-113, February 1999.

Ken Takeuchi, Shinji Satoh, Ken-ichi Imamiya, and Koji Sakui, “A Source-line Programming Scheme for Low Voltage Operation NAND Flash Memories,” IEEE Symp. on VLSI Circuits, pp. 37-38, June 1999.

Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, and Koji Sakui, “A Negative Vth Cell Architecture for Highly Scalable, Excellently Noise-Immune, and Highly Reliable NAND Flash Memories,” IEEE Symp. on VLSI Circuits, pp. 234-235, June 1998.

Shinji Satoh, Hiroyuki Hagiwara, Toru Tanzawa, Ken Takeuchi, and Riichiro Shirota, “A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance,” IEEE International Electron Devices Meeting (IEDM), pp. 291-294, December 1997.

Ken Takeuchi, Tomoharu Tanaka, and Toru Tanzawa, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” International Workshop on Advanced LSI’s, pp. 105-110, July 1997.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, and Hiroshi Nakamura, “Circuit Technology for a Single-1.8V Flash Memory,” IEEE Symp. on VLSI Circuits, pp. 63-64, June 1997.

Tomoharu Tanaka, Toru Tanzawa, and Ken Takeuchi, “A 3.4-Mbyte/sec Programming 3-Level NAND Flash Memory Savein 40% Die Size per Bit,” IEEE Symp. on VLSI Circuits, pp. 65-66, June 1997.

Ken Takeuchi, Tomoharu Tanaka, and Toru Tanzawa, “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories,” IEEE Symp. on VLSI Circuits, pp. 67-68, June 1997.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seeichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, and Kazunori Ohuchi, “A Compact On-Chip ECC for Low Cost Flash Memories,” IEEE Symp. on VLSI Circuits, pp. 59-60, June 1996.

Ken Takeuchi, Tomoharu Tanaka, and Hiroshi Nakamura, “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories,” IEEE Symp. on VLSI Circuits, pp. 69-70, June 1995.