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Kousuke Miyaji, Yasuhiro Shinozuka and Ken Takeuchi, “Zero Additional Process, Local Charge Trap, Embedded Flash Memory with Drain-side Assisted Erase Scheme Using Minimum Channel Length/Width Standard CMOS Single Transistor Cell,” Japanese Journal of Applied Physics (JJAP), vol. 51, no. 4, pp. 04DD02, April 2012.

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